More SMP CuMine Goodness
Posted on: 02/24/2000 02:12 PM

Yep... The HardOCP has done it again. They have more dual CuMine info plastered all over their front page today. Here's the juice...
Intel Claims to have hardware disabled SMP on their FC-PPGA CPU's. I personally think this may be an exaggeration on the part of Intel.
As we all know, i686 CPU's need pins #BR0, and #BR1, these two "Bus Request" pins allow two CPU's to speak with the bus, and each other to get a bus id, or CPU id. In the original white paper that Intel put out for the FC-PPGA at 500 and 550mhz, pin #BR1 was not defined as a pin. (Pin #BR1 is still missing from the Celeron white paper to this day.), however, about a month ago Intel put out the new white paper, Pentium