P.A. Semi Unveils New Processor Family
Posted on: 10/31/2005 03:47 PM

After more than two years of stealth development, P.A. Semi, a founding member of Power.org, recently unveiled its PWRficient processor family: a new microprocessor developed using a Power Architecture license from IBM. The PWRficient processor is a 64-bit scalable, multicore processor family that delivers high performance with very little power consumption, offering up to a ten-fold performance-per-watt advantage over the industry, with the first dual-core chip consuming just 5 to 13 watts.

"The next wave of microprocessor innovation is contingent on solving the problem of dramatically increased power consumption," said cofounder, president, and CEO Dan Dobberpuhl. "We chose to develop our PWRficient processor on the Power Architecture because its scalability, high-performance capabilities, and robust community of developers would help us achieve our goal of a breakthrough performance-per-watt."

The PWRficient processors address the multibillion-dollar Power Architecture-based high-performance embedded and computing markets. The unique system-on-chip architecture and design -- underpinned by 50 patents filed and pending -- delivers high performance (up to 2.5GHz per-core) at phenomenally low power consumption (5 to 13 watts typical at 2 GHz).

Beyond performance per watt, the PWRficient processor delivers key breakthroughs in cost and throughput efficiency. PWRficient processors are the first processors in their class to integrate what is typically a three- to five-chip-set platform into a single chip, called a "platform processor." Not only does the integration of the cores, memory, south bridge, and high-speed I/O onto one chip dramatically reduce the cost of silicon and power consumption, but it also delivers high throughput at low latency.

The first PWRficient chip, the PA6T-682M, which dissipates between just 5 to 13 watts, depending upon the application, is a dual-core implementation running at 2GHz with two DDR2 memory controllers, 2MB of L2 cache, and a flexible I/O subsystem that supports eight PCI Express controllers, two 10 Gigabit Ethernet XAUI controllers, and four Gigabit Ethernet SGMII controllers sharing 24 serdes lanes. It will sample in the third calendar quarter of 2006, with single-core and quad-core versions due in early and late 2007, respectively, and an eight-core version planned for 2008.

The 150-strong P.A. Semi team is headed by Dan Dobberpuhl, the acclaimed lead designer of the DEC Alpha series of microprocessors, the ultra-power-efficient StrongARM microprocessors, and the first commercial multicore processors with the SiByte 1250. Also on board are former AMD Fellow Jim Keller and former Intel Fellow Peter Bannon. Both were also previously at DEC.

http://www.power.org/news/articles/pasemi_processor/


Printed from 2CPU.com (http://www.2cpu.com/contentteller.php?ct=news&action=story&page=pa_semi_unveils_new_processor_family.html)