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2CPU.com » News » February 2004 » Itanium Gamble not Paying Off?

Itanium Gamble not Paying Off?

Posted by: Jim on: 02/29/2004 05:32 AM [ Print | 24 comment(s) ]

David was kind enough to send in this story discussing Intel's "gamble" on Itanium and whether or not that project is paying off.

In its biggest strategic mistake in a decade, Intel has spent an estimated $2 billion creating a high-speed computer chip, the Itanium, that most customers don't want and don't need.

Intel executives say there is no reason to rush to the lifeboats.

"In the second half of 2003, we saw usage triple," said Lisa Graff, director of Intel's Itanium group, referring to corporate use of Itanium. She said Intel expects sales to double in 2004.

I'm sure this will probably create some debate and discussion. Take a look.

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Tessel8
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#27234 Posted on: 02/29/2004 11:50 AM

Nah.... Itanium is poised now to drive forward with some larger adoption.

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jeh
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#27235 Posted on: 02/29/2004 12:51 PM

It may be "poised for it" but there are no new reasons to think it will happen. The magically brilliant compilers that are supposed to make EPIC live up to its promises are still missing in action, nearly ten years after the instruction set was defined. Even if Intel drops the prices to compete with their own Xeons, the Xeon (or Opteron) remains a better choice for almost all buyers.

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jhaislet
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#27236 Posted on: 02/29/2004 03:31 PM

Like I said a couple months ago, Itamium is sinking, and sinking fast, but the captains at intel won't jump ship. To this day, they're still sinking hundreds of thousands of dollars in this 2 Billion dollar lead weight adrift in the ocean. Money can only keep you floating for so long. Maybe microsoft will be next...dropping them down a notch or two would be good for everyone!

I really like that quote "we saw usage triple". Umm yeah, I build computers on the side as a way of earning a bit of spending money (seriously, I do). In 2001, I built 2 computers. In 2003, I built 6!!! Welp, guess I can retire to Tahiti and live up the good life now right? My business did triple! :rolleyes:

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jeh
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#27237 Posted on: 02/29/2004 03:56 PM

Given that HP was a partner with Intel in the development of Itanium (and the killing of Alpha), HP's decision to sell Opteron-based servers must really sting at Intel.

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jhaislet
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#27238 Posted on: 02/29/2004 04:12 PM

In addition to the Intel sting, HP obviously has more intel "inside" (no pun intended

information than joe public. So HP jumping ship means it must be messy inside the itanic devision right now.

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duraid
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#27239 Posted on: 02/29/2004 05:58 PM

Originally posted by jeh
It may be "poised for it" but there are no new reasons to think it will happen. The magically brilliant compilers that are supposed to make EPIC live up to its promises are still missing in action,

That's not really true. I was surprised to see that the latest Intel C/C++ compiler software pipelined ray/triangle intersection for the fairly substantial program "povray", without the programmer needing to give ANY itanium-specific hints.

What does that mean? Just compiling and running povray, my 1300MHz Itanium 2 rendered a little test scene just over *twice* as quickly as a 2GHz G5, using IBM's xlc.

The compilers aren't missing in action, they're a free download. http://developer.intel.com

Even if Intel drops the prices to compete with their own Xeons, the Xeon (or Opteron) remains a better choice for almost all buyers.

The thing is that neither Xeon nor Opteron have any room left to scale architecturally. Many of the performance enhancing features of Xeon and Opteron (e.g. SMT, integer multiply, SSE3) have yet to be added. Do you have any suggestions as to how the Xeon or Opteron could be improved, short of going dual-core? If you do, please write them down, Intel and AMD will both be listening!

Something that Intel keep saying, but that people keep ignoring, is that Itanium processors are on a significantly steeper performance curve than Xeon/P4/P3/Opteron/Athlon. So far, there have only been three real "points" on this curve - Itanium 1, 0.18 Itanium 2 and 0.13 Itanium 2. Have no doubt that when Itanium hits 0.09, it will be the fastest CPU on the planet. Not that anything is competition for the faster 0.13 Itanium 2s around today!

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i_wolf
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#27240 Posted on: 02/29/2004 08:32 PM

Interesting, Povray twice as fast as a dual G5 ??? Very interesting. I assume thats with the latest Intel ICC ????
I would imagine that G5 performance should be significantly higher in this 'test' for want of a better adjective, when they autovectorise XLC like Intel's compiler do with ICC. autovectorisation could even make the G5 beat out the Itanium very handily, due to the potency of Altivec. This is a nice trump card that hasn't been dealt yet in a lot of software. AFAIK, presently the only way to guarantee use of altivec engine is to actually hard code in software calls, or use API's that are already present. I couldn't find much information on the level of support if any for altivec in PovRay. Also the only bench's i saw with XLC with Povray were using -O3 instead of -O5 on the beta public XLC compilers... i would be very interested to see how G5 compares presently using the release version1.0 of XLC at -O5 even ignoring the autovectorisation which is still not present.
Still this is really interesting.

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The Doctor
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#27241 Posted on: 03/01/2004 02:08 AM

Originally posted by duraid

Something that Intel keep saying, but that people keep ignoring, is that Itanium processors are on a significantly steeper performance curve than Xeon/P4/P3/Opteron/Athlon. So far, there have only been three real "points" on this curve - Itanium 1, 0.18 Itanium 2 and 0.13 Itanium 2. Have no doubt that when Itanium hits 0.09, it will be the fastest CPU on the planet. Not that anything is competition for the faster 0.13 Itanium 2s around today!

Hmm... frankly I am dubious about a processor that for the past couple of years has left even its fans saying "yes, okay, so maybe it's not great now, but it will be six months/a year/18 months down the line when they ramp up production/scale up the architecture/double the cache/drop the process size/speed up the bus/dance the bolero, just you wait and see!". Probably true, of course - as long as Xeons, Opterons, G5s et al. don't advance at all during that same period of time.

And, err, isn't the Opteron on an even steeper curve than the Itanium, given that there's only been one version of it thus far?

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duraid
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#27242 Posted on: 03/01/2004 03:43 AM

Originally posted by The Doctor
Hmm... frankly I am dubious about a processor that for the past couple of years has left even its fans saying "yes, okay, so maybe it's not great now, but it will be six months/a year/18 months down the line when they ramp up production/scale up the architecture/double the cache/drop the process size/speed up the bus/dance the bolero, just you wait and see!". Probably true, of course - as long as Xeons, Opterons, G5s et al. don't advance at all during that same period of time.

But the 0.18 Itanium 2 was the fastest CPU available when it was launched, and was for several months thereafter. The 0.13 Itanium 2 was once again the fastest CPU around when launched last year, and it *still is*. Don't get me wrong - the Itanium 2 *is great now* - for the work I do, and a lot of "heavy CPU grunt work" in general, it's the best CPU you can get.

And, err, isn't the Opteron on an even steeper curve than the Itanium, given that there's only been one version of it thus far?

No, because the Opteron is just another K7. Architecturally, it is almost identical. It's just small tweaks here and there, paths are widened to 64 bits, and there is new I/O. But at it's heart, the Opteron is just another Athlon. Not at all like P4 vs P3, for example.

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duraid
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#27243 Posted on: 03/01/2004 04:38 AM

Originally posted by i_wolf
Interesting, Povray twice as fast as a dual G5 ??? Very interesting. I assume thats with the latest Intel ICC ????

That's right, but careful when you say "dual G5". I was testing only one Itanium 2 (in a dual box) vs one G5 (in a dual box).

I would imagine that G5 performance should be significantly higher in this 'test' for want of a better adjective, when they autovectorise XLC like Intel's compiler do with ICC. autovectorisation could even make the G5 beat out the Itanium very handily, due to the potency of Altivec. This is a nice trump card that hasn't been dealt yet in a lot of software.

No, no, no. This is the "point" of EPIC. You don't *vectorize* loops, you pipeline them. Damn, I really need to write up that Itanium FAQ I promised I would. Well, maybe in a couple of weeks I hope...

But what the hell, I can always cut+paste later, so here goes. Allow me to try and explain why EPIC is more advanced than SSE/AltiVec/etc.

In a normal vectorizing CPU (SSE3, AltiVec, etc..) suppose you have a loop like this:

for(int i=0; i<128; i++) {
a=b+c;
}

then many compilers (xlc, Intel's C, etc) will "vectorize" this loop. What that means is, the compiler will spit out instructions like this:

for(int i=0; i<128; i+=4) {
a[i, i+1, i+2, i+3] = b[i, i+1, i+2, i+3] + c[i, i+1, i+2, i+3];
}

The loop happens four times faster because instead of adding elements of the arrays b+c 128 times, it adds 4 entries at a time ("vectors"), so it only has to do 32 adds. Assuming that everything is in cache etc, the loop should go 4 times faster.

OK, that's cool. This kind of stuff (doing the same simple thing, such as addition, to lots and lots of numbers) is quite common, so vectorization helps, particularly in multimedia etc.

But suppose we change the inital simple loop, to something like this:

for(int i=0; i<128; i++) {
if(c>3.2)
c=8.4;
else
b=log(c);
a=b+c;
}

Now we've got a comparison and a function call inside the loop. On any vectorizing CPU (AltiVec, Opteron, whatever) you're stuck. This loop will execute in serial, because the compiler can't tell beforehand what the result of the comparisons will be. And even if it could, the loop would run slower every time it had to set one of the elements to 8.4 (that would be an extra instruction just in itself, at least halving the speed of the loop.) And things would get *much* worse when it has to call the "log" function: no other element of the loop could be processed until log was called. There are hacky ways around this (which the compiler can't do automatically: for example, you could do all the comparisons first, compute all the log values using a vectorized scheme, do the additions, then overwrite the appropriate values) but even that could be easily "broken": if the last line read something like a=b[i-1]+c[i-2], for example, even this couldn't work.

On Itanium, it's a totally different story. All the loops I have shown you can be *pipelined*. Not vectorized (it is very rare to see vectorized itanium code actually). It's a bit hard to explain how this works without being able to draw a picture, but I'll try and use the following analogy.

With vectorization, you have a smart "vector unit" guy you can talk to. He's smart because not only can he add two numbers together, but he can add *pairs* of numbers or even 16 small numbers together, very quickly. Just as fast as he would take to add two numbers. The problem is, once you ask him to do something, he can't be interrupted. And when he's working, he doesn't talk to the rest of the CPU. So if you have 16 numbers to add up - no problem. But if you have something even *slightly* more complex - for example, "add up these 16 numbers, but if any of them are negative, compute their sine and add that instead", the vector guy can't help you. Because he can't usefully do comparisons, or compute sine(), or anything like that. So in something like PPC970 or Pentium 4, you have a vector guy, an ALU guy, a memory guy, and that's it. They all do their thing - even at the same time - but they can't talk to each other so easily. This is oversimplifying things a bit, but the guts of it are there.

With Itanium, you don't have just one guy. You have (in Itanium 2) six guys to talk to. And they can only do one thing at a time. But they're smart, because they can do *anything*. And they can talk to each other *really* easily. So for the complex loop above:

for(int i=0; i<128; i++) {
if(c>3.2)
c=8.4;
else
b=log(c);
a=b+c;
}

here's what happens on Itanium. The compiler goes to the first guy: "OK, you start first. Compare the number c to 3.2 and tell the second guy the answer." Then it tells the second guy "listen to what the first guy tells you. If he says "true", make c 8.4. But if he doesn't, call the log function on c." To the third guy, it goes "as soon as the second guy is done, compute a. But if he's off computing the log function, don't wait for him, just go back to the first guy and start again."

There are six "instruction slots" (guys) on Itanium, but we've used only three. Typically, the compiler would then tell guys 4,5 and 6 do just do the same thing, but start from another point in the loop.

OK. This is a really bad description and sounds stupid. I should have just stopped being lazy and drawn a diagram. But this technique is called "software pipelining" and I'm sure if you look around the web enough, you'll find a much better explanation. Bottom line is this: vectorization works, but only for simple loops (loops that do simple things, I mean). Software pipelining gets you the same result, but it works on simple loops *and* really complex loops that have conditional code, complex internal data dependencies, and even some function calls.

That's why povray goes so fast on Itanium. The loops inside povray are too complex to vectorize, but they're no problem for software pipelining.

What's the catch? To get this technique, you have to use a good compiler. Intel's compiler, HP's compiler and ORC (an open source one) will software pipeline. I'm not sure if Microsoft's compiler will, but I am pretty sure it doesn't. GCC certainly doesn't, but the GCC guys are slowly trying to fix it so it can (ask again in a couple of years...)

AFAIK, presently the only way to guarantee use of altivec engine is to actually hard code in software calls, or use API's that are already present. I couldn't find much information on the level of support if any for altivec in PovRay. Also the only bench's i saw with XLC with Povray were using -O3 instead of -O5 on the beta public XLC compilers... i would be very interested to see how G5 compares presently using the release version1.0 of XLC at -O5 even ignoring the autovectorisation which is still not present.
Still this is really interesting.

That was using the release compiler (on both platforms). And you're quite right, to use vectorization well, it is often better to get the programmer to do it manually. But there's no such need on Itanium, usually. Sometimes (like povray) the compiler can just figure everything out (or at least figure *enough* out...) by itself. At worst, sometimes you just need to give the compiler little hints (like inserting lines before loops going "umm, please software pipeline this loop...."). These hints don't break the code on other platforms. (unlike AltiVec, where unless you carefully made sure that altivec code was only built on Mac machines, your program wouldnt compile any more on other computers...)

OK, just hit the web and oh, the irony. There is a nice description of software pipelining on Apple's website:

http://developer.apple.com/hardware/ve/software_pipelining.html

The irony is that Apple hardware doesn't support software pipelining explicity. (that's the E in EPIC....) They're just "faking" it: the programmer has to manually write code that "pretends" he has a CPU like Itanium, and this also helps superscalar CPUs like Pentium and Opteron and POWER. But these CPUs are only a little superscalar. Nothing like the 6-issue every clock cycle (no matter what) Itanium 2.

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ozric100
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#27244 Posted on: 03/01/2004 04:48 AM

The Opteron is a huge jump from the XP line of CPUS. What tech papers have you been looking at? The Opteron scales very well in every test I have seen published, If I were Intel I would be very frightened about how things are going. Scaling to 128 procs is one thing but for 2 -4 way systems Intel has nothing on the Opterons PnP ratios.

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duraid
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#27245 Posted on: 03/01/2004 04:59 AM

Originally posted by ozric100
The Opteron is a huge jump from the XP line of CPUS. What tech papers have you been looking at? The Opteron scales very well in every test I have seen published, If I were Intel I would be very frightened about how things are going. Scaling to 128 procs is one thing but for 2 -4 way systems Intel has nothing on the Opterons PnP ratios.

Tech papers? ISSCC

Seriously though, the Opteron isn't a huge jump from the XP line. An XP with Opteron's caches and memory controller would perform similarly, clock-for-clock, on x86 code. The design of the Opteron and XP aren't really different at all. Yes they're different, but it's nothing like P3 vs P4 or even POWER3 vs POWER4. Opteron and Athlon are similar.

What's a PnP ratio?

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ozric100
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#27246 Posted on: 03/01/2004 05:13 AM

Price / Performance

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rmn
oh my, it's huge!

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#27247 Posted on: 03/01/2004 05:52 AM

Originally posted by duraid
What does that mean? Just compiling and running povray, my 1300MHz Itanium 2 rendered a little test scene just over *twice* as quickly as a 2GHz G5, using IBM's xlc.

That's nice. Now how fast does it run a real, full-featured 3D animation package, like 3DS MAX, Softimage, Maya, Lightwave, etc.? I don't think many studios render their scenes in POV.

Originally posted by duraid
An XP with Opteron's caches and memory controller would perform similarly, clock-for-clock, on x86 code. The design of the Opteron and XP aren't really different at all.

They are quite different. Apart from the built-in memory controller, the extra (and wider) registers and SSE2 support (which are enough to make them quite different), there are some other changes. There's a new new instruction type (double dispatch), that replaces several instructions that the Athlon XP had to do via vector path (micro code). This speeds up multiplications, pops and pushes. The branch selectors / counters are also different, and the schedulers, register files and speculative instruction lists are bigger. On top of that, the K8 architecture supports SMP and multi-core natively.

If this is "really not different at all", I don't know what qualifies as "different"... :rolleyes:

RMN
~~~

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i_wolf
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#27248 Posted on: 03/01/2004 07:18 AM

That was a great explanation duraid. However, just to add to what you were saying. Merely saying that because the Itanium issues 6 definite instructions per clock tick, can be somewhat misleading. when you talk of piplelines and super piplining, you also have to look at the instruction types and instrucion sizes. AFAIK (correct me if im wrong) RISC (POWER) instructions are much smaller and simpler than EPIC instructions and are executed much faster because they are more efficient. Again i'm no expert on Itanium, but i would love to get my hands on one.
According to the white papers, if software is properly optimized for G5 PPC970 , (according to arstechnica as well), it has a theoetical instruction issue per clock of 8. Which can be realised by optimised code and good compilers like XLC which are very young at the moment. More often its issue count is 5 - 6. However as you pointed out the Itanium is a guaranteed 6 every time.
But the POWER 4 design is somewhat similar to the ideology behind Itanium, they have extremely wide pipelines, thats why i was so surprised to hear you had such a big performance difference. I mean, the internal structure of the PPC970 is extremely wide. They have dual full complex int units, dual full complex fpu, dual altivec all of which can operate independently. SSE2 on P4 (not sure opteron) can not operate independently of the FPU units. Also the dual ALU on P4 is a simple and complex design. Similar to the opteron with its 3 fpu pipelines. I think isn't it 2 simple and one complex on the Opteron??? I am genuinely just very surprised to hear that there is such a big difference in POV RAY.... very interesting.
Regarding the issuing 6 instructions at once... I always assumed that it ran the other instructions in parallel as a brute force mechanism around branch mis predictions. In other words for that if statement, one pipeline would calculate one result of the if, and another would calculate the other result of the if and at the end one would be discarded. you would have 6 instructions guaranteed going through your pipeline, however at the end of the pipeline for ever clock tick, the cpu will have done potentially 3 useful instructions while the others will be discarded. So while 6 instructions can go through as you rightly said, the majority of instructions that do go through are not efficient as they are discarded.
Duraid, have you modified many Open Source apps your self, to as you put it ' give the compiler hints to parallelise the code'. ??? Im interested to hear what type of speed ups you got from these???
Rgs,
i_wolf

Hung like a donkey. Go like a horse!

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Tessel8
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#27249 Posted on: 03/01/2004 11:04 AM

Originally posted by jhaislet
In addition to the Intel sting, HP obviously has more intel "inside" (no pun intended information than joe public. So HP jumping ship means it must be messy inside the itanic devision right now.

I believe if you ask HP, you would see that they consider the opteron stuff they are doing complementary to their Itanium produces, and that this doesn't signal a shift of strats at all. I would imagine they would say they are testing the waters with Opteron because some folks have ask for them. They are interested in making money and keeping people buying HP boxes. If someone is really set on a opteron system, I image they would want to sell it to them rather than their competitors. Business is business, and they may sell the product even if they don't really care that much about it :-).

Tessel8 - Game System - Misc System - Workstation *Not speaking for anyone but myself :-)

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Tessel8
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#27250 Posted on: 03/01/2004 11:16 AM

Originally posted by jhaislet
To this day, they're still sinking hundreds of thousands of dollars in this 2 Billion dollar lead weight adrift in the ocean. Money can only keep you floating for so long. Maybe microsoft will be next...dropping them down a notch or two would be good for everyone!

I really like that quote "we saw usage triple". Umm yeah, I build computers on the side as a way of earning a bit of spending money (seriously, I do). In 2001, I built 2 computers. In 2003, I built 6!!! Welp, guess I can retire to Tahiti and live up the good life now right? My business did triple! :rolleyes:

Well, lets see, there has been public statements that Intel shipped more than 100k Itaniums (Itanium2s actually). That would be a few more than six

. Now, if you look at the price that new Itanium2's go for, the number will probably come out to be a measureable portion of the "2 billion dollars" of investment you are refering to... so they may not be in the red as much as folks think.

Tessel8 - Game System - Misc System - Workstation *Not speaking for anyone but myself :-)

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jrv-austin
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#27251 Posted on: 03/01/2004 11:47 AM

Originally posted by i_wolf
Again i'm no expert on Itanium, but i would love to get my hands on one.

Alas, there

Tyan K8W S2885, 2x Opteron 248, 8GB ECC DDR400, 3ware 8506-8 mirrored 2x Raptor 74, 2x 7k250 HP zx6000 1x 1.5 GHz 6MB Itanic2

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jrv-austin
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#27252 Posted on: 03/01/2004 12:40 PM

Originally posted by Tessel8
Well, lets see, there has been public statements that Intel shipped more than 100k Itaniums (Itanium2s actually). That would be a few more than six . Now, if you look at the price that new Itanium2's go for, the number will probably come out to be a measureable portion of the "2 billion dollars" of investment you are refering to... so they may not be in the red as much as folks think.

If you assume that every Itanic sold was the top-dollar US$5,000 version then the total lifetime Itanic revenue is US$500 million. It's very likely Intel spends more than that on Itanic each year.

My view is that elitism has really hurt Itanic marketing. They've essentially proven to me that it is not profitable for Intel to sell a chip aimed solely at high-end supercomputer apps.

I think they should squarely aim at the low end server market, selling US$1,000 Itanic chips for departmental file and database servers, web servers, etc. The marketing line is to sell it as the same price as a premium Xeon solution, with better performance and far more headroom. It is not cannibalizing the product line to try to move people up! Xeon

Tyan K8W S2885, 2x Opteron 248, 8GB ECC DDR400, 3ware 8506-8 mirrored 2x Raptor 74, 2x 7k250 HP zx6000 1x 1.5 GHz 6MB Itanic2

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jrv-austin
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#27253 Posted on: 03/01/2004 02:00 PM

Originally posted by duraid
The compilers aren't missing in action, they're a free download. http://developer.intel.com /

Those are 30-day free trials.

Is this Intel compiler the best right now for ia64? Any problems with reliability? Any sign it can take advantage of ia64 speculation? Is the ia64 compiler an ia64 app or x86?

The thing is that neither Xeon nor Opteron have any room left to scale architecturally. Many of the performance enhancing features of Xeon and Opteron (e.g. SMT, integer multiply, SSE3) have yet to be added. Do you have any suggestions as to how the Xeon or Opteron could be improved, short of going dual-core? If you do, please write them down, Intel and AMD will both be listening!

Well, I'm not quite ready to give upon x86 - they've got quite a track record at pulling the rabbit out of the hat. Who expected to get even this far? But heroics aren't going to be enough someday.

Out-of-order execution is the biggest thing in my mind that Itanic isn't doing yet. OoO makes it practical to issue three or even four bundles at once. Rather than stall on memory loads there may well be other instructions that can be run. After all, it is OoO and register renaming that allow smaller loops to perform on x86 similarly to Itanic's software pipelining (since the memory ports are always kept busy, and results from each iteration appear as fast as the loads and computation allow).

Something that Intel keep saying, but that people keep ignoring, is that Itanium processors are on a significantly steeper performance curve than Xeon/P4/P3/Opteron/Athlon. So far, there have only been three real "points" on this curve - Itanium 1, 0.18 Itanium 2 and 0.13 Itanium 2. Have no doubt that when Itanium hits 0.09, it will be the fastest CPU on the planet. Not that anything is competition for the faster 0.13 Itanium 2s around today!

It's not clear that Prescott got much boost from 90nm, and suffered severely from heat for its troubles. 90nm is not a universal panacea, at least not when you don't haves silicon-on-insulator in the toolkit.

PS. For the code below you might post the compiler output. That if ought to be hard on Itanic too; I'm having a hard time imagining how they avoid stalling in each iteration to do the cmp, especially with an else clause.


for(int i=0; i<128; i++) {

  if(c>3.2)

    c=8.4;

  else

    b=log(c);

  a=b+c;

}

Tyan K8W S2885, 2x Opteron 248, 8GB ECC DDR400, 3ware 8506-8 mirrored 2x Raptor 74, 2x 7k250 HP zx6000 1x 1.5 GHz 6MB Itanic2

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i_wolf
labhair dom as gaelige

Posts: 2097
Joined: 2002-11-19

#27254 Posted on: 03/01/2004 10:07 PM

Again jvr-austin, thanks for taking the time for such a good reply.
Very interesting. I didn't know that much about programming Itanium, little to nothing about it. Now you and duraid have got my interest peaked. I had a little read over of the Itanium white paper over at Intel. From an architectural point of view the notion of EPIC has been around for years (think it goes back to 60's). It's interesting that such an old concept has not really been implemented well before now.

Hung like a donkey. Go like a horse!

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Idol Observer
Aspiring Duallie

Posts: 108
Joined: 2004-02-07

#27255 Posted on: 03/01/2004 11:33 PM

Originally posted by jrv-austin
If you assume that every Itanic sold was the top-dollar US$5,000 version then the total lifetime Itanic revenue is US$500 million. It's very likely Intel spends more than that on Itanic each year.

My view is that elitism has really hurt Itanic marketing. They've essentially proven to me that it is not profitable for Intel to sell a chip aimed solely at high-end supercomputer apps.

I think they should squarely aim at the low end server market, selling US$1,000 Itanic chips for departmental file and database servers, web servers, etc. The marketing line is to sell it as the same price as a premium Xeon solution, with better performance and far more headroom. It is not cannibalizing the product line to try to move people up! Xeon

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jrv-austin
Registered User

Posts: 257
Joined: 2004-01-19

#27256 Posted on: 03/02/2004 12:18 AM

Originally posted by i_wolf
Again jvr-austin, thanks for taking the time for such a good reply.
Very interesting. I didn't know that much about programming Itanium, little to nothing about it. Now you and duraid have got my interest peaked. I had a little read over of the Itanium white paper over at Intel. From an architectural point of view the notion of EPIC has been around for years (think it goes back to 60's). It's interesting that such an old concept has not really been implemented well before now.

There were a number of commercial VLIW companies in the 1980s, all of which failed. This is one reason Itanium was viewed suspiciously at its beginning. Of course Multiflow etc didn't have Intel Inc as a sugar-daddy. It

Tyan K8W S2885, 2x Opteron 248, 8GB ECC DDR400, 3ware 8506-8 mirrored 2x Raptor 74, 2x 7k250 HP zx6000 1x 1.5 GHz 6MB Itanic2

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Idol Observer
Aspiring Duallie

Posts: 108
Joined: 2004-02-07

#27257 Posted on: 03/02/2004 12:35 AM

Originally posted by jrv-austin
This is one reason Itanium....

Hooray.

2CPU.com » News » February 2004 » Itanium Gamble not Paying Off?

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Itanium Gamble not Paying Off?

Posted by: Jim on: 02/29/2004 05:32 AM [ Print | 24 comment(s) ]

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