McKinley, by contrast, uses an eight-stage core pipeline. Intel contends, however, that the faster front-side bus, more on-chip memory and redundant logic resources will more than make up for the processor's lag in clock speed.

integrating Level 3 cache on-chip was the best way to address latency. In that way, memory access to the outermost cache memory can be done in 12 clock cycles compared with 24 cycles when the Level 3 is a separate device, providing 32 gigabytes per second of bandwidth. And Intel isn't stopping there: Madison, a pin-compatible follow-on to McKinley, will have 6 Mbytes of L3 cache.