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TR and the Tiger MPX

Posted by: Hooz on: 03/07/2002 02:30 PM [ Print | 16 comment(s) ]

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Kampf Pixelated Posts: 553 Joined: 2000-04-21

#14421 Posted on: 03/07/2002 07:48 PM A system fortified with the creamy smoothness of SMP, on the other hand, simply will not slow down. It's friction-free computing. There's nothing else like it. Yes, a good OS can multitask well with one CPU, but as always, some things are just better done in hardware. With SMP, you can run a few game servers in the background while you compute unaffected in the foreground. Or rip and compress MP3s A couple Apple products and a bizarre ASUS S479 box.

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Funkstar Registered User Posts: 33 Joined: 2002-02-03

#14422 Posted on: 03/07/2002 08:45 PM great review it still didn't clear up wheather it will run with 2 x XP's. they say the Tyan 'won't officially sanction' the use of XP's but all they tryed was 1 x MP and 1 x XP...../me confused... If you look at it wrong, a big, electronic hand will reach out of the screen and grab you by the collar while the motherboard chastises you for even thinking about overclocking. This is a serious computer, fool! just about fell off my chair reading that one

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JEC252 Too much time on my hands Posts: 3697 Joined: 2001-05-23

#14423 Posted on: 03/07/2002 09:15 PM nitpicking "Unlike Intel's multiprocessor systems, AMD's multiprocessor systems give each CPU its own, dedicated front-side bus. A shared front-side bus has been a bottleneck in traditional desktop SMP systems, especially in Pentium III systems where the FSB only offers 133MB/s of bandwidth." Is it just me, or was I under the impression that a 133 MHz bus gave it 1 Gb/s of bandwith. Not to mention that with the PIII-S and PIII Xeon, a rock-solid FSB is more of an asset than a fast one. This has been, until recently, one of the things holding the Xeon back. "The Tiger MP was a good board, but it didn't quite light up the enthusiast's mobo scene, despite packing two Once again we've saved civilization as we know it. And the good news is, they're not gonna prosecute!

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Kampf Pixelated Posts: 553 Joined: 2000-04-21

#14424 Posted on: 03/07/2002 10:25 PM The Intel GTL bus shares a single frontside bus between two processors, at whatever speed the FSB is. The AMD/DEC/Alpha EV6 bus, used on the MPX, has an individual, full speed, full bandwidth bus for EACH CPU to the Northbridge chip. This lets each CPU talk to the Northbridge without cramping the other chip's space. A shared front-side bus has been a bottleneck in traditional desktop SMP systems, especially in Pentium III systems where the FSB only offers 1.06GB/s of bandwidth Looks like he didn't proofread enough On the dual XP side, i wouldn't be suprised to see additional benches with two XPs... A couple Apple products and a bizarre ASUS S479 box.

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Edwardo Registered User Posts: 125 Joined: 2000-07-16

#14425 Posted on: 03/07/2002 10:44 PM A great review from Damage as always. We can always expect great things from TR though. I expecially liked the review because he touched upon the intangibles of a dual system which I think is important for everyone. After all, not all of us are graphics designers. Some of us are just plain mean to any system and may really benefit from having two processors to balance the load. "Hand in glove, the sun shines out of our behinds..no it's not like any other love..." -Smiths circa 1985

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JEC252 Too much time on my hands Posts: 3697 Joined: 2001-05-23

#14426 Posted on: 03/07/2002 10:47 PM Originally posted by Kampf The Intel GTL bus shares a single frontside bus between two processors, at whatever speed the FSB is. True, but there are also backside busses. These are what allow the cache to run at 256 bits while the rest of the bus runs at a mear 64 bits. On EV6, the L2 cache is on the FSB where it's limited in speed. On GTL, L2 cache is on the BSB where it can operate asynchronous the FSB clock. Look at it this way ... to transfer data to the core as directly as possible from the FSB. The Athlon must pull it over the FSB, into the L2 cache and through the L2 cache bus. In a PIII, it does a fetch and it's there. In fact, the PIII can pull data from the L2 cache and from the FSB simultaneously, while the Athlon must always pull from the L2 cache. Actually, if anybody cares, the "front" in FSB and "back" in BSB comes from the Slot 1 package, where the bus running through the front side of the package ran at 66/100/133 MHz and the bus running through the backside of the package ran at clock/2 (or clock/3*2, if it was a late 300 or any 333 MHz chip). The term was kept when the cache moved on die, and as such is still valid today. Once again we've saved civilization as we know it. And the good news is, they're not gonna prosecute!

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Kampf Pixelated Posts: 553 Joined: 2000-04-21

#14427 Posted on: 03/08/2002 12:14 AM Ok, i think i know what you're hung up on. I'm talking about the FSB on the motherboard, not the CPU. The L2 cache is on the chip, not on the motherboard! MPX has two independet busses, one for each CPU, right to the NB chip. GTL has one shared bus to the NB. We're not discussing chip architecture, but motherboard architecture. A couple Apple products and a bizarre ASUS S479 box.

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timekills Satellite rider Posts: 526 Joined: 2000-08-17

#14428 Posted on: 03/08/2002 05:18 AM Then there's the USB problem. Thanks to a bug in AMD's 768 south bridge chip, all AMD 760MPX motherboards currently have a broken USB controller. Holy frejoles! I can't believe someone would say such a preposterous and obviously unfounded statement! Thank goodness this wasn't mentioned on a well-respected site like 2CPU.com some time ago. That might have raised some serious issues. Waitminute.... I may not agree with your opinion, but I will defend to the death your right to express it.

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JEC252 Too much time on my hands Posts: 3697 Joined: 2001-05-23

#14429 Posted on: 03/08/2002 05:38 AM Originally posted by Kampf Ok, i think i know what you're hung up on. I'm talking about the FSB on the motherboard, not the CPU. The L2 cache is on the chip, not on the motherboard! MPX has two independet busses, one for each CPU, right to the NB chip. GTL has one shared bus to the NB. We're not discussing chip architecture, but motherboard architecture. L2 cache once wasn't on the chip, and in many cases still isn't (PIII Xeon, anyone?) In fact, the Intel placed the L2 cache where it sits on an Athlon ... back with the Pentium and Pentium MMX. On the motherboard there are two busses, but when you have an entire system running there's still two, in a dual PIII/Xeon system you have three. As much as a fast FSB is nice, it isn't everything, especially when it's shared with an already bottlenecked L2 cache. This was the design reasoning behind GTL, GTL+, AGTL and AGTL+ ... Intel discovered with the Pentium that L2 cache, when on the system bus, severely strained it. And, if you want to get technical, there's nothing preventing someone from taking a slotket, modifying it to take two Celeron 300 (non-A's) and dropping a whole bunch of full-speed L2 cache on it. Nothing whatsoever. This was the original design purpose behind the BSB ... for large servers where two processors would share the same L2 cache and then would be plugged into the motherboard as a two-way SMP Slot 1 card. Once again we've saved civilization as we know it. And the good news is, they're not gonna prosecute!

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CamoAlien SMP Christian Posts: 782 Joined: 2001-07-10

#14430 Posted on: 03/08/2002 06:13 AM All this talk about Slot 1 processors is making me wish even more that Intel had not dropped this packaging! What is wrong with large corporations these days? Anyways, I like the review. It was very well done (even if I don't particularly like tyan) compared to those of other MP(X) boards by other sites. 's are :cool: My Rigs fold for humanity alongside team # 3074 Tyan Thunder 2500 / SGI Zx10 Hardware Compatibility List 73 de a Ham OPR

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Timshel Registered User Posts: 131 Joined: 2000-10-23

#14431 Posted on: 03/08/2002 08:53 AM ...currently have a broken USB controller. Thank goodness this wasn't mentioned on a well-respected site like 2CPU.com some time ago. That might have raised some serious issues. Couldn't help noticing this myself... Hehehe Slackware Linux Server - Squid Proxy, Samba, FTP Server(vsftpd) | MSI 694D | 2x733@810 | 2x256MB Crucial CL2 | 32MB GF2-MX | 80GB Maxtor ATA133 | Intel Pro100B | BENQ 32/20/32 Proud Winner of Heavy Water ! See pics |AT7-Max2|Athlon XP 2100|Abit Siluro TI4600|36GB WD Raptor|3x80GB Maxtor ATA133 - RAID 5|SB Audigy|Lite-on SOHW812 xFlash 832s|Samsung 172x LCD|Windows XP SP2

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JEC252 Too much time on my hands Posts: 3697 Joined: 2001-05-23

#14432 Posted on: 03/08/2002 09:22 AM Originally posted by CamoAlien All this talk about Slot 1 processors is making me wish even more that Intel had not dropped this packaging! What is wrong with large corporations these days? Lol, no-one really likes that it's gone except the bean counters who want to save $3 a processor. With the Slot 1 processors with full-speed on-die L2 cache they might as well have been Socket 370, but the Slot formats were originally very well thought out and, if they had been executed better would have really rocked the world. Just look at the technical specifications: Slot 1: up to two CPU dies, two L1 caches and an L2 cache Slot 2: up to four CPU dies, four L1 caches and an L2 cache Slot A: one CPU die, one L1 cache and an L2 cache Now, if someone had come out with a Slot 1 processor with two 733 MHz dies and instead of on-die cache, the full-speed cache of the PIII Xeons ... who here wouldn't buy it? Just imagine that computing power in any old single 133 MHz Slot 1 board ... two 733 MHz processors, 2 Mb shared L2 cache and a dedicated interprocessor and L2 bus running at 733 MHz and 256 bits ... and throw a pair of those in a Tiger 133. Now, if Intel had done that, how many people here would honestly be considering REALLY getting an Athlon MP? Once again we've saved civilization as we know it. And the good news is, they're not gonna prosecute!

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dryrye Registered User Posts: 299 Joined: 2001-09-10

#14433 Posted on: 03/08/2002 10:00 AM Sorry to rain on everybody's parade... but as long as the motherboard is not listed on AMD's "Recommended Motherboards", http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_869_965^2340,00.html , wouldn't that invalidate the processors' warranty!!!! How come nobody ever mentions that in a review?

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peteb solittletimesomuchtodo Posts: 330 Joined: 2001-12-06

#14434 Posted on: 03/08/2002 10:48 AM Running a Duron 1GHz and a Duron 1.1GHz Lian-Li PC-76|Tyan S2466N|2xXP1700|2GB Reg ECC|Enermax651/301 Dual PSU|5x36ES Raid5 ICP Vortex GDT8623RZ|3Ware 7500-8|4xWD1000JB Raid5, 2xMaxtor80GB Raid0|SB Audigy|WinXPSP1|More PCs

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ambit LoveYourFruit Posts: 1243 Joined: 2000-10-15

#14435 Posted on: 03/08/2002 08:41 PM Originally posted by JEC252 L2 cache once wasn't on the chip, and in many cases still isn't (PIII Xeon, anyone?) Just nit-picking here (actually, making sure my understanding is correct) That the Xeon's based on the 133Mhz FSB which only have 256k L2 cache (the 'fake' xeons) have their cache on-die. And the 'real' xeons with 512k or more still have it off-die? I think..?

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JEC252 Too much time on my hands Posts: 3697 Joined: 2001-05-23

#14436 Posted on: 03/08/2002 09:43 PM Originally posted by ambit Just nit-picking here (actually, making sure my understanding is correct) That the Xeon's based on the 133Mhz FSB which only have 256k L2 cache (the 'fake' xeons) have their cache on-die. And the 'real' xeons with 512k or more still have it off-die? I think..? Correct. The PII/III Xeons at 400/100/512, 400/100/1024, 400/100/2048, 450/100/512, 450/100/1024, 450/100/2048, 500/100/512, 500/100/1024, 500/100/2048, 550/100/512, 550/100/1024, 550/100/2048, 700/100/1024, 700/100/2048 and 900/100/2048 all run on a 100 MHz FSB and have off-die L2 cache running on a BSB at full processor clock speed and a 256 bit wide data bus, making it as fast as the on-die cache on the 133 MHz bus PII/III Xeons and PIII E's. Once again we've saved civilization as we know it. And the good news is, they're not gonna prosecute!